1. Field of the Invention
This invention relates to a method of laying out traces on a substrate and the layout for connection of a semiconductor chip to a printed wiring board and the like.
2. Brief Description of the Prior Art
Semiconductor integrated circuits are formed in semiconductor chips which contain the electrical circuits. Bond pads are generally disposed on the chip with the chip being mounted within a package and the bond pads being connected by wires to lead frame fingers or the like which extend externally of the chip. The package, after fabrication, is generally secured to a printed wiring board with the lead frame fingers or the like connected to bonding regions on the printed wiring board. The package as well as the electrically conductive members which transfer the signals from the chip to the printed wiring board add to the undesirable loads (i.e., inductances, noise, crosstalk, etc.) which the chip may see with the magnitude of these undesirable loads increasing with increasing chip operating frequency.
A typical package may include a substrate having a cavity which contains a chip within the depression. Bond wires couple bond pads on the chip to individual copper traces on the substrate, the copper traces each extending to an electrically conductive aperture or via which extends through the substrate to an electrically conductive ball pad and a solder ball. The vias and ball pads are formed in a matrix array having plural rows and columns of vias which are located adjacent one or more of the sides defining the depression. Adjacent vias and ball pad centers in a row or a column are spaced apart from each other by a distance defined herein as a “ball pitch”, this distance being the dimension from the center of one via or ball pad to the center of the adjacent via or ball pad in the same row or in the same column. The “ball pitch” between all adjacent vias or ball pads in the same row or in the same column is the same. The solder ball is soldered to a pad on a printed wiring board in standard manner as discussed in the above noted copending application to make the connection from the chip to the printed wiring board pad.
The copper traces as well as the bond wires, electrically conductive regions in the vias and surrounding wiring and packaging add additional circuitry to the electrical circuit which bring to the circuit additional resistances, inductances and capacitances. The layout of the circuitry and especially the layout of the traces materially affects the performance of the chip, this being particularly material in the case of differential wiring pairs wherein pairs of wires carry the same or similar signals but are out of phase with each other. It is therefore apparent that a layout is highly desirable which minimizes the above noted problems of the prior art.